TP28054(8052+64Kflash) Port0 drive 補充說明

Because TP2804 is following MCS-51 compatible,

so describe according to specification MCS-51 (http://www.intel.com/design/mcs51/manuals/272383.htm ). “Port 0 differs in not having internal pullups. The pullup FET in the P0 output driver is used only when the Port is emitting 1s during external memory accesses. Otherwise the pullup FET is off. Consequently P0 lines that are being used as output port lines are open drain. Writing a 1 to the bit latch leaves both output FETs off, so the pin floats.” Therefore can know Port0 really can be regarded as open drain and used in output. The following figure shows:

Figure: MCS-51 I/O Ports

[POWER ON RESET]

 Generally speaking, TP2804 HQNE must have one valid reset at power on (At least two clock period). If reset signal is in immature cases, all behaviors are unpredictable and unstable. The customer using TP2804HQNE is while expecting at power on and let this in case of open-drain of Port0 work can’t be guaranteed even more.
  So describe according to specification MCS-51, “NOTE: The port pins will be in a random state until the oscillator has started and the internal reset algorithm has written 1s to them.” and “To ensure a valid reset the RST pin must be held high long enough to allow the oscillator to start up plus two machine cycles.” The MCS-51 is the same situation too.

Port0 really can be regarded as open drain and used in output, but that is must have one valid reset at power up.